In order to decrease power consumption in CMOS (Complementary Metal Oxide Semiconductor) circuits using MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), it is most effective to lower the power supply voltage. However, merely lowering the power supply voltage would cause the drive current of MOSFETs to lower, resulting in a lower operating speed of the circuit. This phenomenon is known to become noticeable as the power supply voltage becomes a triple or less of the threshold of the transistor. Although this phenomenon can be prevented by lowering the threshold, doing so would give rise to a problem of increases in off-leak current of MOSFETs. Therefore, the lower limit of the threshold is defined within a range over which the above problem does not occur. This in turn defines the limits of power consumption reduction since the lower limit of the threshold corresponds to the lower limit of the power supply voltage.
Conventionally, there has been proposed a dynamic-threshold operation transistor (hereinafter, referred to as DTMOS) which employs a bulk substrate for alleviation of the above-mentioned problem (Japanese Patent Laid-Open Publications HEI 10-22462, Novel Bulk Threshold Voltage MOSFET (B-DTMOS) with Advanced Isolation (SITOS) and Gate to Shallow-Well Contact (SSS-C) Processes for Ultra Low Power Dual Gate CMOS, H. Kotaki et al., IEDM Tech. Dig., p. 459, 1996). The aforementioned DTMOS has a characteristic of a capability of high drive current with low power supply voltage by virtue of its effective threshold lowering in an ON state. The reason why the effective threshold of DTMOS lowers in the ON state is that the gate electrode and the well region are electrically short-circuited.
The principle of operation of the N-type DTMOS is explained below. It is noted that the P-type DTMOS operates similarly with the polarity reversed. In the N-type MOSFET, when the gate electrode voltage is at a low level (in an OFF state), the P-type well region voltage is also at a low level, the effective threshold has no differences from normal MOSFETs. Therefore, the off current value (off-leak) is the same as in the case of normal MOSFETs.
On the other hand, when the gate electrode voltage is at a high level (in an ON state), the P-type well region voltage is also at a high level, the effective threshold lowers by the substrate-bias effect, so that the drive current increases compared with those of normal MOSFETs. Therefore, large drive current can be obtained with low power supply voltage while low leak current is maintained.
In a DTMOS, the gate electrode and the well region are electrically short-circuited. Therefore, as the gate electrode voltage changes, the well voltage also changes similarly. This accordingly requires the well region of each DTMOS to be mutually electrically isolated from the well regions of its neighboring MOSFETs. For this reason, the well region is made up of a shallow well region and a deep well region which are different in polarity from each other. Furthermore, the shallow well regions of the respective DTMOS' are electrically isolated from one another by a device isolation region.
As a conventional method for suppressing off-leaks in low voltage drive and still obtaining high drive current, there has been a method in which the well-bias voltage is changed between standby and active states (Japanese Patent Laid-Open Publications HEI 6-216346 and 10-340998).
Hereinafter, a MOSFET in which in which the well bias is changed between standby and active states will be expressed as substrate-bias variable transistor.
The principle of operation of the N-type substrate-bias variable transistor is explained below. It is noted that the P-type substrate-bias variable transistor operates similarly with the polarity reversed. In an N-type substrate-bias variable transistor, when the circuit is in an active state, a 0 V or positive voltage (with a source voltage referenced) is applied from a bias generation circuit to the P-type well region. With a positive voltage applied to the P-type well region, the effective threshold lowers due to a substrate-bias effect, and the drive current increases as compared with the case of normal MOSFETs. When the circuit is in a standby state, on the other hand, a negative voltage is applied from the bias generation circuit to the P-type well region. As a result of this, the effective threshold increases due to the substrate-bias effect, and the off-leak decreases as compared with normal MOSFETs or DTMOS'.
Generally, in a circuit using substrate-bias variable transistors, whether the active state or the standby state is effectuated is selected every circuit block. This is because providing the bias generating circuit for each device causes the number of devices and the circuit area to increase considerably. From these reasons, the P-type well region of an N-type MOSFET is common within a circuit block (the case is the same with the N-type well region of a P-type MOSFET). Accordingly, in a circuit block which is in an active state, a 0 V or positive voltage is applied to the well regions of all the N-type MOSFETs, so that the off-leak increases as compared with normal MOSFETs or DTMOS' (the case is the same also with the P-type MOSFETs).
In the circuit using substrate-bias variable transistors, the MOSFETs have to share a well region. For this purpose, the depth of the bottom face of the device isolation region is set deeper than the depth of the junction between the source regions and drain regions of the MOSFETs and their shallow well region and, at the same time, shallower than the depth of the lower end of the well region.
There has been disclosed a technique in which the DTMOS and the substrate-bias variable transistor are combined together to make the best of their respective advantages (Japanese Patent Laid-Open Publication HEI 10-340998).
FIG. 11 shows a cross-sectional view of a device fabricated by this technique. Referring to FIG. 11, there are shown, with reference numerals having the following denotations, a semiconductor P-type substrate 311, an N-type deep well region 312, a P-type deep well region 313, an N-type shallow well region 314, a P-type shallow well region 315, a device isolation region 316, an N-type MOSFET source region 317, an N-type MOSFET drain region 318, a P-type MOSFET source region 319, a P-type MOSFET drain region 320, an N+ diffusion layer 321 for providing contact with an N-type shallow well region, a P+ diffusion layer 322 for providing contact with a P-type shallow well region, a gate insulator 323, a gate electrode 324, a P-type substrate-bias variable transistor 325, an N-type substrate-bias variable transistor 326, an N-type DTMOS 327, a P-type DTMOS 328, a well-bias input 329 for the P-type substrate-bias variable transistor, a well-bias input 330 for the N-type substrate-bias variable transistor, and a fixed bias input 331 for the P-type deep well region. In addition, although not shown, the gate electrode 324 and the P-type shallow well region 315 are electrically short-circuited in the N-type DTMOS 327, and the gate electrode 324 and the N-type shallow well region 314 are electrically short-circuited in the P-type DTMOS 328.
In the DTMOS' 327 and 328, the voltages of the shallow well regions 314 and 315 change with the voltage of the gate electrode 324. In order to prevent changes of the voltages of the shallow well regions 314 and 315 from affecting shallow well regions 314 and 315 of other devices, deep well regions 313 and 312 opposite in conductive type to the shallow well regions 314 and 315 are formed under those shallow well regions 314 and 315. Moreover, a device isolation region 316 is formed at enough depth to electrically isolate shallow well regions 314 and 315 of mutually neighboring devices. By doing so, the shallow well regions 314 and 315 are electrically isolated from shallow well regions 314 and 315 of neighboring devices. Meanwhile, shallow well regions of the substrate-bias variable transistors 326 contained in one circuit block have to be provided in common. Therefore, under the P-type shallow well regions 315 of the N-type substrate-bias variable transistors 326 in FIG. 11, is formed the P-type deep well region 313, which is integrated with a P-type shallow well region 315 to form a common well region. To this P-type common well region 313, 315, a voltage that differs between active and standby states is given via the well-bias input 330 for the N-type substrate-bias variable transistor 326. In order to prevent any effects on devices of other circuit blocks or DTMOS portion, the N-type deep well region 312 is formed further deeper in the substrate, by which the P-type deep well region 313 is electrically isolated. Under the shallow well region 314 of the P-type substrate-bias variable transistor 325 in FIG. 11, is formed the N-type deep well region 312, which is integrated with the N-type shallow well region 314 to form a common well region 312, 314. To this N-type common well region 312, 314, a voltage that differs between active and standby states is given via the well-bias input 329 for the P-type substrate-bias variable transistor 325.
FIGS. 12 and 13 show the procedure of forming the deep well regions 312, 313 of this conventional semiconductor device. As shown in FIG. 12, with photoresist 332 used as a mask, dopant injection for forming the P-type deep well region 313 is performed, and then dopant injection for forming the N-type deep well region 312 further deeper is performed. Next, as shown in FIG. 13, with the photoresist 332 used as a mask, dopant injection for forming the N-type deep well region 312′ is performed. In this case, the depth of the N-type deep well region 312′ is set to a level similar to the depth of the P-type deep well region 313. By these steps, the N-type deep well regions 312 and 312′ are integrated together, by which the P-type deep well region 312 is electrically isolated.
In this way, the substrate-bias variable transistors 325, 326 and the DTMOS' 327, 328 are formed on the same substrate 311, making it possible to realize a circuit making the best of their respective advantages.
As shown in FIG. 11, in the conventional semiconductor device in which the DTMOS' 327, 328 and the substrate-bias variable transistors 325, 326 are combined together (Japanese Patent Laid-Open Publication HEI 10-340998), although the P-type deep well regions 313, 313, can be electrically isolated, the N-type deep well region 312 is common within one substrate 311. Therefore, although the circuit block of the N-type substrate-bias variable transistors 326, 326, . . . can be formed plurally within the same substrate 311, the circuit block of the P-type substrate-bias variable transistor 325, . . . cannot be formed plurally. For this reason, the circuit block of the P-type substrate-bias variable transistors 325, cannot be divided properly into active circuit blocks and standby circuit blocks. For example, when only part of the P-type substrate-bias variable transistors 325, 325, . . . need to be put into active state, the entirety of the P-type substrate-bias variable transistors 325, 325, . . . would come into an active state, causing the leak current to increase. As a result, the power consumption would increase.
Also, the conventional semiconductor device, in which the N-type deep well regions 312 are integrated together within the substrate 311, has a PN junction of a large area comparable to the area of the whole substrate 311. That is, a very large electrostatic capacity is parasitically present. Therefore, changing over between active and standby states in a circuit block of the P-type substrate-bias variable transistors 325, 325, . . . causes the bias of the whole N-type deep well region 312 to change, which in turn causes large amounts of charges to be charged and discharged. As a result, the power consumption increases.
Furthermore, in the foregoing semiconductor device, putting the P-type substrate-bias variable transistors 325, 325, . . . into the active state (i.e., giving a voltage lower than the power supply voltage to the N-type deep well region 312) makes it more likely that a latch-up phenomenon is induced. In an NPNP type structure having routes passing through the N-type shallow well region 314 of the P-type DTMOS 328, the P-type deep well region 313, the N-type deep well region 312 and the P-type shallow well region 315 of the N-type DTMOS 327, a case (undershoot) is discussed where a bias lower than ground voltage is applied to the N-type shallow well region 314 of the P-type DTMOS 328. In the DTMOS 328, in which the gate electrode 324 and the shallow well region 314 are electrically connected to each other, it can occur that a bias not more than the ground voltage is applied to the N-type shallow well region 314 of the P-type DTMOS 328 through the gate electrode 324. In this case, a forward voltage is applied to the junction between the N-type shallow well region 314 of the P-type DTMOS 328 and the P-type deep well region 313, so that electrons are injected into the P-type deep well region 313. The electrons injected into the P-type deep well region 313 reach the N-type deep well region 312, causing the voltage of the N-type deep well region 312 to decrease. With the voltage of the N-type deep well region 312 decreased, holes are injected from the P-type shallow well region 315 of the N-type DTMOS 327 into the N-type deep well region 312. The holes injected into the N-type deep well region 312 reach the P-type deep well region 313, causing the voltage of the P-type deep well region 313 to increase. With the voltage of the P-type deep well region 313 increased, electrons injected from the N-type shallow well region 314 of the P-type DTMOS 328 into the P-type deep well region 313 increase more and more. Through iterations of these steps (with a positive feedback applied), an abnormal current flow in the NPNP structure, giving rise to a latch-up phenomenon. In this connection, if a voltage lower than the power supply voltage has been applied to the N-type deep well region 312 from the beginning (i.e., if the P-type substrate-bias variable transistor 325 has been in an active state), the latch-up phenomenon is more likely to occur. Further, also when the P-type substrate-bias variable transistor 325 comes into a standby state (i.e., also when a voltage higher than the power supply voltage is applied to the N-type deep well region 312), it become more likely that a latch-up phenomenon is induced. In this case, a large inverse-bias is applied to the junction between the P-type shallow well region 315 of the N-type DTMOS 327 and the N-type deep well region 312, as well as to the junction between the P-type deep well region 313 and the N-type deep well region 312. This causes a punch-through to occur between the P-type shallow well region 315 of the N-type DTMOS 327 and the P-type deep well region 313, triggering the occurrence of a latch-up phenomenon in the NPNP structure. As to the route of the latch-up, in addition to the above-mentioned one, such an NPNP structure may also be mentioned as one including a route which passes the drain region 318 of the N-type DTMOS 327, the P-type shallow well region 315 of the N-type DTMOS 327, the N-type deep well region 312 and the P-type deep well region 313. Thus, largely changing bias of the N-type deep well region 312 makes it difficult to control the latch-up phenomenon. As a result, the device reliability deteriorates.